thanks for hint with sigrok project.
I'm using SUMP and the build in spi analyse function to debug SPI communication.
The only ICs on MISO line are two MCP3208 adcs which are controlled by separate CS lines.
I tried different spi modes. the one from the picture above is:
only axo and euxo pcb the max. working clock freq. for SPI is FPCLK/16.
with 74hc14 (2xinverting before SPI ICs) and 4 devices on SPI bus with a sum of 30cm connection lines the max clock freq. is around FPCLK/64.
for mcp3208 spi communcation the datasheet say that I have to choose between CPOL = 0, CPHA = 0 or CPOL=1, CPHA=1.
The adc don't need a constant clock rate to work. it only needs an on/off to work. (described at section "6.2 Maintaining Minimum Clock Speed/page19 datasheet)
here is one overview where the last channel of one adc should be read. this channel is directly connected to VDD.
The one which is printed out by axo patcher console only axo+euxo core (spi connection traces = max. 12cm).
the second turn is with bus pirate sniffing communication(+ max. 15cm of spi connection).
axoloti setup spi mode 0, FPCLK/256, format=LSB and spi commands are send/received synced with "spiExchange".
I supposed this too. therefore I tried the schmitt trigger to clean up the signals and reduce the slew rates to a minimum of time. I also tried some small caps (10pF,22pF,1nF,10nF) and resistors (10R, 22R, 100R, 1K, 10K) in series as lp filter or single on miso and clock line but no improvements.
I've read some things about "wellenwiederstand" (engl. wave resistance?), hf-trace layout and rf filters on this documentation and many thread at mikrocontroller.de
the current euxo spi trace layout is not ideal (gnd is between every trace but long trace distances and one via per trace).
So I cut the clock trace at the start and end point on the pcb and soldered a single wire from axoloti directly to the clk pin of the mcp3208 socket (white cable).
after this I can also connect the bp cable to the unit and receive right values…so this wire (dia. ~1,1mm) improves the stability of spi communication.
but if the bp is also connected, axo received weird messages on mosi. the bp receives spi message correctly on the longer connection if only this device is connected to the spi line.
other spi ICs like 74hc595 which tested in combination with the euxo setup works without any issues. So MOSI/SCLK transmitting is working.
my analog osci (hameg hm203-6) don't have any storage function. A cheap DSO osci is on my ordering list for a long time.
I can confirm that the axoloti and mcu is very tough against little mistakes.
edit1: I tried to use the Low level SPI driver (spi_lld_init etc.) but can't get it working.